1. Field of the Invention
The present invention relates to a semiconductor device and to a method of manufacturing the same. More particularly, the present invention relates to the die of a semiconductor device, and to a method of manufacturing the same.
2. Description of the Related Art
Semiconductor devices generally comprise a semiconductor chip (die) and a package for the chip. The semiconductor chip, in turn, generally includes a substrate (portion of a wafer) and circuit patterns disposed on the substrate. A major goal in the manufacturing of today's semiconductor devices is to make the devices thinner and lighter. To achieve this, the packages of the devices or the semiconductor chips must be made smaller. Examples of small packages that have recently been developed are the Wafer Level Package (WLP) and the Surface Mount Package (SMP). Reducing the size of the semiconductor chip requires the forming of finer circuit patterns and/or reducing the thickness of the substrate.
Among these methods, increasing the amount of back-lap of the wafer to reduce the overall thickness of the semiconductor chip (die) is the most basic and essential way of ultimately reducing the size of the semiconductor chip. For example, the thickness of a wafer of a DRAM device after back-lap currently exceeds 250 μm, although the wafers from which DRAMS are made are gradually becoming thinner.
However, as the wafer of a semiconductor chip becomes thinner, a die-warpage phenomenon in which the die tends to bend and warp laterally and/or longitudinally becomes more severe. Die-warpage causes the surface of a semiconductor device to become uneven, as shown in FIG. 1.
More specifically, a fully fabricated semiconductor device has a plurality of conductive and isolating patterns and insulating layers stacked one atop the other on a substrate. The die warps due to stress in an upper and/or lower portion of the stacked structure, i.e., due to resultant stress applied to a semiconductor substrate by the layers that constitute the stacked structure. The layers which cover the entire surface of the semiconductor substrate cause the most severe stress. Such layers include interlayer insulating layers (ILD and an IMD layers), passivation layers, and PhotoSensitive PolyImide (PSPI) layers. Die-warpage will now be described in more detail using the PSPI layer as an example.
FIG. 2A is a plan view of a conventional semiconductor device including a PSPI layer. FIG. 2B is a sectional view of the semiconductor device, taken along line AA′ of FIG. 2A, and FIG. 2C is a sectional view of the semiconductor device taken along line BB′.
Referring to FIGS. 2A, 2B and 2C, electrodes used as connection pads 12 are formed in the uppermost surface of a substrate 10. Also, fuse lines 14 are formed in portions of the substrate 10 located beneath the uppermost surface thereof. A passivation layer 20 for protecting the substrate 10 from humidity and/or impurities is disposed on the substrate 10. The passivation layer 20 may be a composite layer comprising a silicon oxide layer, such as a HDP oxide layer 22, and a silicon nitride layer such as a PE-SiN layer 24. A PSPI layer 30 is disposed on the upper surface of the passivation layer 20 to prevent soft errors caused by α-particles and to protect the substrate 10 from shock during subsequent processes, e.g., a packaging process.
First through-holes 40 extend through the PSPI layer 30 and the passivation layer 20 in alignment with the connection pads 12 at the upper surface of the substrate 10, thereby exposing the connection pads 12. Second through-holes 50 extend through the PSPI layer 30 and the passivation layer 20 as aligned with the fuse lines 14, thereby exposing the fuse lines 14. The arrangement of the through-holes 40, 50 depends on the positions and arrangement of the connection pads 12 and the fuse lines 14. FIG. 2A diagrammatically illustrates the through-holes 50 with respect to a current DRAM device. In this device, the second through-holes 50 are arranged in first and second rows 52, 54 that extend longitudinally and laterally in the die, respectively.
Table 1 shows the amount of die-warpage measured in semiconductor devices of the type shown in FIGS. 2A through 2C, wherein the substrates of the devices have various thicknesses t1(thickness after back-lap) and the PSPI layers 30 have various thicknesses t3. Each of the devices was a rectangular 256M DDR DRAM device having a die of 4.9916 mm×10.047 mm.
TABLE 1Thickness t1 of substrate (μm)75100150200Thickness t3043.823.23.30.6of PSPI3.047.626.47.61.8layer (μm)6.554.234.412.02.4
Referring to Table 1, the die-warpage was greatest in those devices having the thinnest substrates (smallest thickness t1), and the thickest PSPI layer (greatest thickness t3). The greater the thickness t3 of the PSPI layer 30, the greater is the tensile stress. The die is severely warped due to such tensile stress. The PSPI layer 30 is formed by depositing a photosensitive polyimide material to a thickness of about 10 μm on the passivation layer 20, exposing and developing the resultant layer, and then baking the layer to imidize the material and remove impurities therefrom. The baking process, however, reduces the thickness of the layer to about 6˜7 μm. Accordingly, a large compressive stress is applied to the substrate 10.
A method of reducing die-warpage caused by the PSPI layer is disclosed in Japanese Laid-open Patent No. 11-307525, entitled “Semiconductor device and a manufacturing method thereof.” In this method, two kinds of polyimide materials are used to form a polyimide layer. Specifically, a substrate is sequentially coated with a non-photosensitive polyimide material and a photosensitive polyimide material. The non-photosensitive polyimide material that contacts the substrate has a relatively small compressive stress. Thus, the stress exerted on the substrate is relatively low. However, the process of forming this PSPI layer is relatively complex because two polyimide materials are used. Also, the two polyimide materials have different compressive stresses. Accordingly, it is difficult to control the amount of die-warpage. Moreover, the extent to which the underlying non-photosensitive polyimide layer can be removed during an etching process and the profile of the underlying non-photosensitive polyimide layer cannot be precisely controlled.
Also, referring to Table 1, die-warpage occurs even when no PSPI layer 30 is formed. It is believed that the stress caused by layers of material constituting the stacked structure on the substrate 10 cause the die-warpage. That is, the die-warpage occurs prior to forming the PSPI layer 30. For example, interlayer insulating layers such as ILDs and IMDs and the passivation layer 20, covering the entire surface of the substrate, may cause the die-warpage. Therefore, die-warpage is an unavoidable problem in any semiconductor device formed by stacking a plurality of layers of different material.
Because the die-warpage applies stress to conductive and non-conductive patterns and electrical devices disposed on the substrate, the reliability of the semiconductor device is degraded. Also, any die-warpage will almost certainly cause defects to occur during subsequent processes. For example, if a die that is warped is packaged, the packaging process might not package the die effectively, i.e., the die is apt to be broken by a minor shock when the device is handled, for example. Furthermore, an uneven layer of material, resulting from die-warpage, makes it difficult to precisely carry out a photolithographic process of forming a pattern on the semiconductor substrate.